1. Field of the Invention
The present invention relates to a current drive circuit for supplying a driving current to a display panel.
2. Description of the Related Art
A conventional current drive circuit for supplying a driving current to a display panel is disclosed by, for example, Japanese Patent Application Kokai No. 2005-6250.
FIG. 1 of the accompanying drawings is a circuit diagram of a current drive circuit. The current drive circuit supplies a driving current to a current drive type display device 1. The current drive circuit includes a reference current generating part 10, a digital-to-analog (DA) converter 20, a plurality of electric current latching parts 301 to 30n (n denotes an integer of two or more), and a timing controlling part 40.
The reference current generating part 10 generates a reference electric current Iref determined from a reference voltage Vref and a basis resistance Rref and generates a bias voltage VB whose magnitude corresponds to the reference electric current Iref. The reference current generating part 10 includes a p-channel MOS (PMOS) transistor 11 connected between a power supply electrical potential VDD and a node N1, a resistance 12 connected between the node N1 and an earth potential GND, and an operational amplifier (OP) 13. The reference voltage Vref is supplied to a first input terminal of the operational amplifier 13. A second input terminal of the operational amplifier 13 is connected to the node N1. A power output terminal of the operational amplifier 13 is connected to a gate terminal of the PMOS transistor 11. The bias voltage VB is supplied from the power output terminal of the operational amplifier 13.
The DA converter 20 generates a display electric current SNK having a magnitude corresponding to a value of display data Din. The display data Din is, for example, 8 bits data. The DA converter 20 includes eight PMOS transistors 210 to 217 and eight corresponding switches 220 to 227. Drain terminals of the PMOS transistors 210 to 207 are connected to a node N2. Gate terminals of the PMOS transistors 210 to 207, to which the bias voltage VB is applied, are connected to the node N2 together. The switches 220 to 227 are connected between a power supply electrical potential VDD and source terminals of the PMOS transistors 210 to 217, respectively. On/OFF switching operation of these switches 220 to 227 is respectively controlled in response to signals b0 to b7 which consist of the 8-bit display data Din. The PMOS transistors 210 to 217 are set so as to generate electric currents whose magnitude are respectively weighed by a factor of 1, 2, 4, 8, 16, 32, 64, and 128 of the reference electric current Iref when the switches 220 to 227 are turned on. In response to the display data Din having a value Di (i denotes the integer from 1 to n), the DA converter 20 generates the display electric current SNK, whose magnitude is represented as Di×Iref, from the node N2 thereof.
The electric current latching parts 301 to 30n have a similar configuration. The electric current latching part 301, for example, includes switches 31 and 32. The switch 31 is connected between the node N2 of the DA converter 20 from which the display electric current SNK is supplied and a node N3 of the electric current latching part 301. The switch 32 is connected between the node N3 and a node N4. These switches 31 and 32 are on-off controlled in response to a write-controlling signal W1 supplied by the timing controlling part 40. The electric current latching part 301 also has an n-channel metal oxide semiconductor (NMOS) transistor 33, a capacitor 34, and an NMOS transistor 35. Drain and gate terminals of the NMOS transistor 33 are connected to the node N3 together. Source terminal of the NMOS transistor 33 is connected to an earth potential GND. The capacitor 34 is connected between the node N4 and the earth potential GND. Gate and source terminals of the NMOS transistor 35 are connected to the node N4 and the earth potential GND, respectively. Drain terminal of the NMOS transistor 35 is connected to a display line of the display device 1 which is driven with a driving current OUT1 passing through the NMOS transistor 35.
The timing controlling part 40 periodically generates write-controlling signals W1 to Wn, which are sequentially supplied to the electric current latching parts 301 to 30n, respectively, in synchronization with the display data Din supplied to the DA converter 20.
An operation of the current driver circuit in FIG. 1 will be described. In the reference current generating part 10, the operational amplifier 13 produces a signal which is in accordance with a difference in voltages applied to the first and second input terminals thereof and supplies the signal to the gate terminal of the PMOS transistor 11. The PMOS transistor 11 is on-off controlled in response to the signal supplied by the operational amplifier 13. A voltage applied to the drain terminal of the PMOS transistor 11 is feed-backed to the second input terminal of the operational amplifier 13, so that the referential voltage Vref is eventually applied to the node N1. The reference electric current Iref flows through the PMOS transistor 11 and the resistor 12, and thus the bias voltage VB applied to the PMOS transistor 1, whose magnitude corresponds to the reference electric current Iref, is applied to the DA converter 20.
The switching operations of the switches 220 to 227 are controlled in response to a value (e.g., D1) of the display data Din supplied to the DA converter 20. A weighed electric current flows to one of the PMOS transistors 210 to 217 connected to the switch 220 to 227 which is turned on. The display current SNK having a magnitude D1×Iref, which corresponds to the value D1 of the display data Din, is supplied from the node N2 of the DA converter 20 through the PMOS transistor 210.
The timing controlling part 40 supplies a write-controlling signal to either one of the electric current latching parts 301 to 30n. The write-controlling signal W1 is supplied to the current latching part 301 to which the display current SNK having a magnitude D1×Iref corresponding to the value D1 of the display data Din is applied. It is to be noted that the write-controlling signals W2 to Wn are not supplied to other electric current latching parts 302 to 30n while the write-controlling signal W1 is supplied to the electric current latching part 301. The switches 31 and 32 of the electric current latching part 301 are turned on in response to the write-controlling signal W1, and thus the display electric current SNK generated by the DA converter 20 flows to the NMOS transistor 33. Accordingly, the driving current OUT1 having a magnitude corresponding to the magnitude of the display electric current SNK, that is, D1×Iref, flows to the NMOS transistor 35. The capacitor 34 is charged to a gate voltage of the NMOS transistor 35 at the time when the switches 31 and 32 are turned on.
When a value of the display data Din changes from D1 to D2, the write-controlling signal W1 supplied by the timing controlling part 40 is stopped, and then a write-controlling signal W2 is supplied to the electric current latching part 302. As a result, a driving current OUT2 whose magnitude is represented as D2×Iref flows to the NMOS transistor 35 of the electric current latching part 302.
On the other hand, the switches 31 and 32 of the electric current latching part 301 are turned off in response to the stop of the write-controlling signal W1, and thus the electric current flowing to the NMOS transistor 33 of the electric current latching part 301 is stopped. The capacitor 34 of the electric current latching part 301 is electrically charged to the gate voltage having a magnitude corresponding to the electric current of D1×Iref, so that the driving current OUT1 keeps flowing to the NMOS transistor 35 of the electric current latching part 301.
The electric current latching parts 301 to 30n, each of which performs in a similar way, generate driving currents OUT1 to OUTn, respectively. The driving currents OUT1 to OUTn whose magnitude correspond to the values D1 to Dn of the display data Din keep flowing to the NMOS transistors 35 of the electric current latching parts 30A1 to 30An, respectively.
However, there are the following difficulties in the above-described current drive circuit. The driving currents OUT1 to OUTn generated by the electric current latching parts 301 to 30n, respectively, vary according to the values of the display data Din. The driving currents OUT1 to OUTn are dependent on the voltages charged to capacitors 34 of electric current latching parts 301 to 30n, respectively. The magnitude of the driving electric currents OUT1 to OUTn are determined from voltages at which the electric current latching parts 301 to 30n are charged when the write-controlling signals W1 to Wn are supplied. Therefore, the voltages charged to the capacitors 34 are required to vary according to new driving currents OUT1 to OUTn while the write-controlling signals W1 to Wn are supplied. However, each of the electric current latching parts 301 to 30n dose not include a circuit for discharging electric charges retained in the capacitor 34 sufficiently. If the driving current having a magnitude zero, for example, is generated in response to the next display data Din, charges retained in the capacitor 34 can not be completely discharged and a voltage at the node N4 is retained at a threshold voltage of the NMOS transistor 33. Therefore, the above-mentioned current drive circuit can not generate the driving currents with high accuracy if the driving currents OUT1 to OUTn are small.
A time period necessary for charging the capacitor 34 is reversely proportional to the magnitude of the display electric current SNK, so that it takes much time to sufficiently the capacitor if the display currents SNK are small. Therefore, there arises a difficulty in speeding up the display speed.